This invention relates to the fabrication of integrated circuit devices and, more particularly, to a method for forming low-resistance contact to silicon in very-large-scale-integrated (VLSI) devices.
It is known to utilize a silicide on silicon to achieve high-conductivity contacts and interconnects in metal-oxide-semiconductor (MOS) VLSI devices. It is also known to interpose a diffusion barrier between the silicide and an overlying aluminum layer to prevent silicide-aluminum or silicon-aluminum interactions. In that way, the likelihood of the multilayer metallization causing harmful effects such as penetration and shorting of extremely shallow junctions in such devices is minimized.
Heretofore, the silicide and diffusion barrier layers included in an MOS VLSI device have typically been formed in separate steps of a device fabrication sequence. This approach is relatively time-consuming and costly. Moreover, this sometimes results in the formation of a deleterious relatively high-resistivity interface between the silicide and barrier layers.
Accordingly, workers in the art have directed efforts at trying to simplify and render more effective the procedure by which the aforedescribed multilayer metallizations are made. It was recognized that such efforts, if successful, had the potential for significantly improving the performance and lowering the cost of MOS VLSI devices.